I have the information (see below).  Not all is relevant to us right now.  The
important point is that for HIGH gain, 1 LSB is lost, for LOW Gain, no
information is lost.  

Costas, you are right.  We do have a global 100 MeV resolution for High Gain.  
I forgot that the bit shifts are all left for the other quantities, so we 
don't loose information.  I think, however that there is another problem.

We have two paths of data.

1) detector -> tec -> fast clear -> FAST_CLEAR_DOTRIGSUM -> DOTEC -> digital values.

2) detector -> cal readout -> caltru -> DOTRIGSUM -> DOTEC -> digital values.

In principle, one should set the LSB to 0 in both paths if the 
HIGH gain is used.  This is trivial as Costas Says.

Also note that FAST_CLEAR_DOTRIGSUM is completely different from the standard 
DOTRIGSUM.  The FAST_CLEAR_DOTRIGSUM must convert a digital value back to a 
real energy.  If this formula is not EXACTLY correct, then energy 
(say 0.001) MeV could be lost.  This lost energy could sometimes give 
a TEC digital value one count lower than the hardware, now our error 
is again one count and we have wasted our time.

We cannot just assume that cutting the LSB will give us the correct answer.  
We must confirm that the fast clear INPUT digital values are the same as what 
comes out of the simulation after DOTEC and after cutting the LSB.

To confirm this one must study in detail the FAST_CLEAR_DOTRIGSUM code.  
I believe it is in several parts and is trying to undo the bit shifting 
scheme detailed below.  

----------------------------------------------------------------------------
From:   VXDESY::BYLSMA      
To:     WODARCZYK
CC:     BYLSMA
Subj:   handleing gain scales in the FC
 
Hi Mike,
        Here is a concise description of what the fast clear does to the 8bit
numbers that it receives from the CFLT.  
 
 
      SCALE    REGION HYBRID?        OPERATION
---------------------------------------------------------------
 
    HIGH GAIN    ALL             Shift right 1 bit   (lsb lost) 
 
    LOW  GAIN   FCAL             Shift left  4 bits
    LOW  GAIN   RCAL             Shift left  2 bits
    LOW  GAIN   BCAL (NO HYBRID) Shift left  2 bits
 
    LOW  GAIN   BCAL (HYBRID):   CLASS   EMC   HAC
                                -------------------
                                   0  | SL 4 | SL4 
                                   1  | SL 2 | SL4 
                                   2  | SL 2 | SL2
 
                                  SEQUENCE   CLASS 
                                 ------------------
                                     0     |   0
                                     1     |   0
                                     2     |   0
                                     3     |   0
                                     4     |   0
                                     5     |   0
                                     6     |   0
                                     7     |   0
                                     8     |   1
                                     9     |   1
                                    10     |   1
                                    11     |   1
                                    12     |   2
                                    13     |   2
                                     .     |   .
                                     .     |   .
                                     .     |   .
                                    26     |   2
                                    27     |   2


   Hybrids are even BCAL slots 0,2,4,6,8,10,12,14 (8L,8R,9L,9R,AL,AR,BL,BR)