Trigger Adder Cards

The Adder Card has 2 principal functions. The first is to continue the process of summing up the energies begun on the TEC. The second is to perform pattern tests on the bits that accompany the energy sums. These pattern tests include counting the number of trigger towers passing each of the energy thresholds, summing up the energy from the threshold test bits in subregions of the region covered by the adder card, and finding isolated muons and electrons.

As shown in Figure 13, there are two 9U high double-width Adder Cards, which are identical in all respects and reside in the middle of the VME crate in positions 10 and 12. One Adder Card is inserted to the right and the other to the left of the split in the J2 and J3 backplanes. They perform several functions, the first of which is to continue the process of obtaining the total E, E$_T$, E$_x$, and E$_y$. The Adder Card also handles clock distribution, recognition of isolated Minimum Ionization events, recognition of isolated Electromagnetic events, comparison of cell energy against preset thresholds, and some simple histogramming (counting) of the individual cell utilization. Most of the logic is ECL to provide the performance required to process data arriving at nearly 1 Gbyte/sec. A short printed circuit card connects the Adder cards together in the front of the crate. This card transfers data and clocks across the split backplane.

Figure: Schematic outline of a CFLT crate including Trigger Adder Cards, TEC's, crate processor card and monitor card. Connections to Fast Clear, CFLTP, and Trigger Sum Cards are also shown.

As a result of their central location, the Adder Cards are used to distribute clocks to the Trigger Encoder cards arrayed on either side. The 96 nsec and 12 nsec clocks are differential ECL signals, fed from the CFLTP on a cable containing only clocks. There is separate, equal-length cabling, from the CFLTP to each of the Adder Cards. The Adder Card generates gated 96, 48, 24, and 12 nsec clocks from the CFLTP 12 nsec clock. These clocks may be stopped and single stepped under VME control. All actions in the crate occur at the time of the rising edge of the 12 nsec clock.

Seven TECs on each half of a trigger crate output their data to the nearest of two adder cards located in the center of the crate. The Adder Cards operate as a master and slave, exchanging data to perform their tasks. They continue adding the digitized $E_{total}$, $E_T$, $E_x$, and $E_y$ for those EMC and HAC channels serviced by the crate, perform local sums using threshold information for the subregions shown in Figure 14, count up numbers of towers passing the various thresholds, and perform pattern tests on the Q, M, and E bits.

Figure: Subregions of the calorimeter trigger regions (0-7 in F/RCAL, 8-F in BCAL).

The pattern logic searches for contained isolated electrons and muons in the interior $5\times 6$ tower section of each $7\times 8$ trigger region and for edge isolated electrons and muons on each of the four remaining sides of the trigger region. The two Adder Cards then send sums of $E_{total}$, $E_T$, $E_x$, $E_y$ to the CFLTP, along with summaries of the number of edge isolated and contained electrons and muons found in the region. The CFLTP further processes this information, and sends its results on to the global first level trigger processor (GFLTP) [2].