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This test loads the test memories with incrementing numbers. The linearization
memories are loaded with specific patterns, and the correct value for that
pattern is expected from the test memory. The data is read from the tower
multiplexor, so the data lines from the 4 towers to the tower multiplexor are
also tested. Since the towers have only 4 bits, only 4 address lines from
LINM to test memories are really tested.