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The Q J2 Test checks the TECs quiet bits by reading the input card.
Both the TEC being tested and its partner TEC are set to a port on the
edge of the crate's region. The Quiet bits for the selected TEC are
toggled and the CFLTP input card is read to see if the quiet edge was
set. The TEC partners are as follows : (0-7), (1-8), (2-9), (3-10),
(4-11), (5-12), (6-13). The partner has all of its Quiet, Electron
and Min. Ionization bits set to provide the maximum quietness possible
for the adder cards edge check. If either partner cannot set one of
these three bits, then both TECs will fail the test since the edge
cannot be quiet. All 4 towers of a TEC have its quiet bits toggled.
To be sure that the quiet bit backplane drivers work for all ports,
the Tower Thresholds test must pass for the TEC. Two edges are
tested, so ports 0 and 6 are checked explicitly.