Crate Address Space

TEC Addresses
Address	TEC
	0	1	2	3	4	5	6
Command Reg.	00064000	000E4000	00164000	001E4000	00264000	002E4000	00364000
Ped Vol.Reg.	00064004	000E4004	00164004	001E4004	00264004	002E4004	00364004
Tower Mux.	00064014	000E4014	00164014	001E4014	00264014	002E4014	00364014
Adder Mux.	00064012	000E4012	00164012	001E4012	00264012	002E4012	00364012
HAC FIFO	00064014	000E4014	00164014	001E4014	00264014	002E4014	00364014
EMC FIFO.	00064018	000E4018	00164018	001E4018	00264018	002E4018	00364018
Delay 01	00064008	000E4008	00164008	001E4008	00264008	002E4008	00364008
Delay 23+45	0006400C	000E400C	0016400C	001E400C	0026400C	002E400C	0036400C
Delay 67	00064010	000E4010	00164010	001E4010	00264010	002E4010	00364010
HAC 1 LINM	00000000	00080000	00100000	00180000	00200000	00280000	00300000
HAC 1 GMA	00020000	000A0000	00120000	001A0000	00220000	002A0000	00320000
HAC 1 GMB	00040000	000C0000	00140000	001C0000	00240000	002C0000	00340000
EMC 1 LINM	00004000	00084000	00104000	00184000	00204000	00284000	00304000
EMC 1 GMA	00024000	000A4000	00124000	001A4000	00224000	002A4000	00324000
EMC 1 GMB	00044000	000C4000	00144000	001C4000	00244000	002C4000	00344000
HAC 2 LINM	00008000	00088000	00108000	00188000	00208000	00288000	00308000
HAC 2 GMA	00028000	000A8000	00128000	001A8000	00228000	002A8000	00328000
HAC 2 GMB	00048000	000C8000	00148000	001C8000	00248000	002C8000	00348000
EMC 2 LINM	0000C000	0008C000	0010C000	0018C000	0020C000	0028C000	0030C000
EMC 2 GMA	0002C000	000AC000	0012C000	001AC000	0022C000	002AC000	0032C000
EMC 2 GMB	0004C000	000CC000	0014C000	001CC000	0024C000	002CC000	0034C000
HAC 3 LINM	00010000	00090000	00110000	00190000	00210000	00290000	00310000
HAC 3 GMA	00030000	000B0000	00130000	001B0000	00230000	002B0000	00330000
HAC 3 GMB	00050000	000D0000	00150000	001D0000	00250000	002D0000	00350000
EMC 3 LINM	00014000	00094000	00114000	00194000	00214000	00294000	00314000
EMC 3 GMA	00034000	000B4000	00134000	001B4000	00234000	002B4000	00334000
EMC 3 GMB	00054000	000D4000	00154000	001D4000	00254000	002D4000	00354000
HAC 4 LINM	00018000	00098000	00118000	00198000	00218000	00298000	00318000
HAC 4 GMA	00038000	000B8000	00138000	001B8000	00238000	002B8000	00338000
HAC 4 GMB	00058000	000D8000	00158000	001D8000	00258000	002D8000	00358000
EMC 4 LINM	0001C000	0009C000	0011C000	0019C000	0021C000	0029C000	0031C000
EMC 4 GMA	0003C000	000BC000	0013C000	001BC000	0023C000	002BC000	0033C000
EMC 4 GMB	0005C000	000DC000	0015C000	001DC000	0025C000	002DC000	0035C000
Test Mem 1	00060000	000E0000	00160000	001E0000	00260000	002E0000	00360000
Test Mem 2	00068000	000E8000	00168000	001E8000	00268000	002E8000	00368000
Test Mem 3	00070000	000F0000	00170000	001F0000	00270000	002F0000	00370000
Test Mem 4	00078000	000F8000	00178000	001F8000	00278000	002F8000	00378000

TEC Addresses : CFLT(Thumbwheel) Numbering
Address	TEC
	7(9)	8(10)	9(11)	10(12)	11(13)	12(14)	13(15)
Command Reg.	004E4000	00564000	005E4000	00664000	006E4000	00764000	007E4000
Ped Vol.Reg.	004E4004	00564004	005E4004	00664004	006E4004	00764004	007E4004
Tower Mux.	004E4014	00564014	005E4014	00664014	006E4014	00764014	007E4014
Adder Mux.	004E4012	00564012	005E4012	00664012	006E4012	00764012	007E4012
HAC FIFO	004E4014	00564014	005E4014	00664014	006E4014	00764014	007E4014
EMC FIFO.	004E4018	00564018	005E4018	00664018	006E4018	00764018	007E4018
Delay 01	004E4008	00564008	005E4008	00664008	006E4008	00764008	007E4008
Delay 23+45	004E400C	0056400C	005E400C	0066400C	006E400C	0076400C	007E400C
Delay 67	004E4010	00564010	005E4010	00664010	006E4010	00764010	007E4010
HAC 1 LINM	00480000	00500000	00580000	00600000	00680000	00700000	00780000
HAC 1 GMA	004A0000	00520000	005A0000	00620000	006A0000	00720000	007A0000
HAC 1 GMB	004C0000	00540000	005C0000	00640000	006C0000	00740000	007C0000
EMC 1 LINM	00484000	00504000	00584000	00604000	00684000	00704000	00784000
EMC 1 GMA	004A4000	00524000	005A4000	00624000	006A4000	00724000	007A4000
EMC 1 GMB	004C4000	00544000	005C4000	00644000	006C4000	00744000	007C4000
HAC 2 LINM	00488000	00508000	00588000	00608000	00688000	00708000	00788000
HAC 2 GMA	004A8000	00528000	005A8000	00628000	006A8000	00728000	007A8000
HAC 2 GMB	004C8000	00548000	005C8000	00648000	006C8000	00748000	007C8000
EMC 2 LINM	0048C000	0050C000	0058C000	0060C000	0068C000	0070C000	0078C000
EMC 2 GMA	004AC000	0052C000	005AC000	0062C000	006AC000	0072C000	007AC000
EMC 2 GMB	004CC000	0054C000	005CC000	0064C000	006CC000	0074C000	007CC000
HAC 3 LINM	00490000	00510000	00590000	00610000	00690000	00710000	00790000
HAC 3 GMA	004B0000	00530000	005B0000	00630000	006B0000	00730000	007B0000
HAC 3 GMB	004D0000	00550000	005D0000	00650000	006D0000	00750000	007D0000
EMC 3 LINM	00494000	00514000	00594000	00614000	00694000	00714000	00794000
EMC 3 GMA	004B4000	00534000	005B4000	00634000	006B4000	00734000	007B4000
EMC 3 GMB	004D4000	00554000	005D4000	00654000	006D4000	00754000	007D4000
HAC 4 LINM	00498000	00518000	00598000	00618000	00698000	00718000	00798000
HAC 4 GMA	004B8000	00538000	005B8000	00638000	006B8000	00738000	007B8000
HAC 4 GMB	004D8000	00558000	005D8000	00658000	006D8000	00758000	007D8000
EMC 4 LINM	0049C000	0051C000	0059C000	0061C000	0069C000	0071C000	0079C000
EMC 4 GMA	004BC000	0053C000	005BC000	0063C000	006BC000	0073C000	007BC000
EMC 4 GMB	004DC000	0055C000	005DC000	0065C000	006DC000	0075C000	007DC000
Test Mem 1	004E0000	00560000	005E0000	00660000	006E0000	00760000	007E0000
Test Mem 2	004E8000	00568000	005E8000	00668000	006E8000	00768000	007E8000
Test Mem 3	004F0000	00570000	005F0000	00670000	006F0000	00770000	007F0000
Test Mem 4	004F8000	00578000	005F8000	00678000	006F8000	00778000	007F8000

	Adder Card
Address	Left	Right
Command Reg.	00380000	00400000
Corners Reg.	00380004	00400004
FIFO delay	00380006	00400006
SLC 0	00388000	00408000
SLC 1	00389000	00409000
SLC 2	0038A000	0040A000
SLC 3	0038B000	0040B000
SLC 4	0038C000	0040C000
SLC 5	0038D000	0040D000
SLC 6	0038E000	0040E000
SLC 7	0038F000	0040F000
SLC 8	00390000	00410000

=10000

TEC VME Registers
Generic Addressing:	<23:19>	Board Base Address, front panel switches
(C0050)	<18:17>	Memory Type, values:
		0= Linearization Memory
		1,2= Geometric Memories A, B
		3= Threshold Tests Memory
	<16:15>	Tower Number: values 0-3 indicate towers 1-4
	<14>	HAC or EMC: 0=HAC; 1=EMC
	<13:1>	Memory address bits
	<0>	not used
Offset (hex)	Register Description
00000-03FFE	Tower 1, HAC	(D0023) Linearization Memory
04000-07FFE	Tower 1, EMC	(D0027)
08000-0BFFE	Tower 2, HAC	(D0024)
0C000-0FFFE	Tower 2, EMC	(D0028)
10000-13FFE	Tower 3, HAC	(D0025)
14000-17FFE	Tower 3, EMC	(D0029)
18000-1BFFE	Tower 4, HAC	(D0026)
1C000-1FFFE	Tower 4, EMC	(D0030)
20000-23FFE	Tower 1, HAC	(D0023) Geometric Memory A (E,ET)
24000-27FFE	Tower 1, EMC	(D0027)
28000-2BFFE	Tower 2, HAC	(D0024)
2C000-2FFFE	Tower 2, EMC	(D0028)
30000-33FFE	Tower 3, HAC	(D0025)
34000-37FFE	Tower 3, EMC	(D0029)
38000-3BFFE	Tower 4, HAC	(D0026)
3C000-3FFFE	Tower 4, EMC	(D0030)
40000-43FFE	Tower 1, HAC	(D0023) Geometric Memory B (Ex,Ey)
44000-47FFE	Tower 1, EMC	(D0027)
48000-4BFFE	Tower 2, HAC	(D0024)
4C000-4FFFE	Tower 2, EMC	(D0028)
50000-53FFE	Tower 3, HAC	(D0025)
54000-57FFE	Tower 3, EMC	(D0029)
58000-5BFFE	Tower 4, HAC	(D0026)
5C000-5FFFE	Tower 4, EMC	(D0030)
60000-63FFE	Tower 1	(D0061) Tower Threshold Tests Memory
68000-6BFFE	Tower 2	(D0062)
70000-73FFE	Tower 3	(D0063)
78000-7BFFE	Tower 4	(D0064)

TEC VME Registers
Offset (hex)	Register Description
64000	Command Register
(C0051)	Board function control R/W
	<31:24>	undefined
	<23>	High Gain Select
		1= Gain 32, 0= Gain 8
	<22:20>	Backplane Port Select, displayed on LEDs
		Valid port values: 0-6; 7 disables output
	<19>	Blocking, 1= Supress energy for the following four
		crossings if High Gain Overflow in current crossing
	<18:16>	Command function, displayed on LEDs; values:
		0= No special function (normal running)
		1= Setup (enable read only)
		2= Setup and Write (enable read and write)
		3= * Test Mode, enable faking FADC output
		4= undefined
		5= * Initialize memories and FIFO
		6,7= undefined
	* Commands 3 and 5 disable VME access to other registers; subsequent
	reads and writes to any board address access the command register
	Hardware ID RO
	<15:8>	undefined
	<7:0>	Hardware ID, unique to board (set via jumpers)
	When writing to the command register, bits <15:0> must be the same as bits <32:16>
64004	Low Gain Pedestal DAC (all low gain channels) WO
(C0068)	12 bit digital to analog converter for pedestal subtraction
	Range: $-2.048~V~\rightarrow +2.048~V$, 1 mV per count
	<31:28>	undefined
	<27:16>	DAC Register
	High Gain Pedestal DAC (all high gain channels) WO
	<15:11>	undefined
	<11:0>	DAC register
	$FFF \rightarrow +2.048~V$
	$BE8 \rightarrow +1.000~V$
	$418 \rightarrow -1.000~V$
	$000 \rightarrow -2.048~V$

TEC VME Registers
Offset (hex)	Register Description
64008	Delay 0,1 WO
(D0071)	Two 6 bit programmable analog delay line registers, 2 ns per count
	<31:14>	undefined
	<13:8>	Delay value, channel 1
	<7:6>	undefined
	<5:0>	Delay value, channel 0
6400C	Delay 2,3 WO
(D0071)	Two 6 bit programmable analog delay line registers, 2 ns per count
	<31:30>	undefined
	<29:24>	Delay value, channel 3
	<23:22>	undefined
	<21:16>	Delay value, channel 2
	Delay 4,5 WO
	<15:14>	undefined
	<13:8>	Delay value, channel 5
	<7:6>	undefined
	<5:0>	Delay value, channel 4
64010	Delay 6,7 WO
(D0071)	<31:30>	undefined
	<29:24>	Delay value, channel 7
	<23:22>	undefined
	<21:16>	Delay value, channel 6
	Adder Mux  -  J2 Backplane Test Register RO
	Multiplexed HAC and EMC card sums of: E, ET, Ex, Ey
	<15:9>	undefined
	<8>	Overflow bit
	<7:0>	Energy

TEC VME Registers
Offset (hex)	Register Description
64014	Tower Tests Mux  -  J3 Backplane Test Register RO
(C0065)	Muliplixed Tower HAC and EMC Threshold Tests, Towers 1-4
	<31:22>	undefined
	<21:19>	Coarse (logarithmic) Energy: T2, T1, T0 bits
	<18>	E (electron) bit
	<17>	M (min ionizing) bit
	<16>	Q (quiet) bit
	Select Pipe 0 R/W
	Latched HAC Energy output of FADC, input to Linearization Memories
64018	Select Pipe 1 R/W
(D0066)	Latched EMC Energy output of FADC, input to Linearization Memories
	<31:25>	undefined
	<24>	Overflow bit
	<23:16>	Energy
	<15:0>	undefined