Pattern Recognition Memory Addressing Format
<14:12>	Slice number, values 0-6
<11>	not latched, not used
<10:1>	Q and EM bit tower input patterns
	Meaning depends the data field, see example below
Addressing for Secondary cycle, data bits <11:8>
<10>	Bottom row flag
<9:3>	Lower and right side Q bits
<2:0>	Pattern code from primary cycle, values 0-7
Addressing for Primary cycle, data bits <3:0>
<10:5>	Central and upper corner Q bits
<4:1>	Central E or M bits