Contents

• Contents
• List of Tables
• List of Figures
• Introduction
• Running the Adder_Test Program
  • Prerequisites for Successful Adder Testing
  • Adder_Test Main Menu
  • Selecting and Running Adder Tests
• Tests and Error Interpretation
  • VME Tests, 0 - 5
  • Tests Using CFLTP Input Cards, Crossing Numbers and Clock Modes, Tests 6 - 20
  • General Functionality Tests, 6 - 7
  • Subregion Tests, 8 through 11
  • Adder Tree Tests, 12 through 16
  • Test 16 - Overflow Correct Test
  • Pattern Recognition Tests, 17 through 20
  • Fast Clear Tests, 21 through 23
• Changing Test Settings and Rebooting Transputers in the Expert Menu
  • Maximum VME Test Error Reporting
  • Rebooting the Transputer Network
  • Changing the CFLT to CFLTP Input Card Mapping
  • Flushing the CFLTP and Looping Clock Trains
  • Changing the Clock Mode for Testing - High Statistics CFLT Tests
  • Changing the Adder Tree TEC mode for Alternating Patterns
• Hints for Debugging
  • CFLTP and CFLTP Cable Related Problems
  • Comments on Backplane Problems
  • So You Think You Have an Adder Problem?
• Loading Test Patterns for Debugging in the Expert Menu
  • Loading Tower Patterns for CFLTP Transfer
  • Displaying Data from the CFLTP
  • Loading Tower Patterns for Fast Clear Transfer
  • Displaying Data from the Fast Clear
  • Looping Fast Clear Transfers and CFLTP Triggers
• Spying on CFLT data from the GFLT in the Expert Menu
• Overview of Source Code and Directories
• Adder VME Registers and Memories
  • Special Control Registers
  • Pattern Recognition Memories
  • Subregion Assignment Memory
• Known Adder Problems and Peculiarities
  • Even Subregion Carry Bit Bleeding
  • Quiet Edge Anomaly - ``Green Towers''
  • Top Corner Edge Assignments - ``Blue Towers''
• Bibliography